EP4SE360F35I4 Datasheet, PDF (72/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

3–16
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
Shift-Register Mode
All Stratix IV memory blocks support shift register mode. Embedded memory block
configurations can implement shift registers for digital signal processing (DSP)
applications, such as finite impulse response (FIR) filters, pseudo-random number
generators, multi-channel filtering, and auto- and cross-correlation functions. These
and other DSP applications require local data storage, traditionally implemented with
standard flipflops that quickly exhaust many logic cells for large shift registers. A
more efficient alternative is to use embedded memory as a shift-register block, which
saves logic cell and routing resources.
The size of a shift register (w × m × n) is determined by the input data width (w), the
length of the taps (m), and the number of taps (n). You can cascade memory blocks to
implement larger shift registers.
Figure 3–14 shows the TriMatrix memory block in shift-register mode.
Figure 3–14. Shift-Register Memory Configuration
w x m x n Shift Register
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
n Number of Taps
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation