EP4SE360F35I4 Datasheet, PDF (63/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
3–7
Overview
Figure 3–4 shows the address clock enable waveform during the write cycle.
Figure 3–4. Address Clock Enable During the Write Cycle Waveform
inclock
wraddress
data
wren
addressstall
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
a0
a1
00
01
an
a0
XX
XX
a2
a3
02
03
a1
00
01
02
XX
XX
XX
XX
a4
a5
a6
04
05
06
a4
a5
03
04
05
Mixed Width Support
M9K and M144K memory blocks support mixed data widths inherently. MLABs can
support mixed data widths through emulation using the Quartus II software. When
using simple dual-port, true dual-port, or FIFO modes, mixed width support allows
you to read and write different data widths to a memory block. For more information
about the different widths supported per memory mode, refer to “Memory Modes”
on page 3–9.
1 MLABs do not support mixed-width FIFO mode.
Asynchronous Clear
Stratix IV TriMatrix memory blocks support asynchronous clears on output latches
and output registers. Therefore, if your RAM is not using output registers, you can
still clear the RAM outputs using the output latch asynchronous clear. Figure 3–5
shows a waveform of the output latch asynchronous clear function.
Figure 3–5. Output Latch Asynchronous Clear Waveform
outclk
aclr
aclr at latch
q
You can selectively enable asynchronous clears per logical memory using the
Quartus II RAM MegaWizard Plug-In Manager.
f For more information, refer to the Internal Memory (RAM and ROM) User Guide.
December 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1