EP4SE360F35I4 Datasheet, PDF (161/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
5–45
PLL Reconfiguration Hardware Implementation
The following PLL components are reconfigurable in real time:
■ Pre-scale counter (n)
■ Feedback counter (m)
■ Post-scale output counters (C0 - C9)
■ Post VCO Divider (K)
■ Dynamically adjust the charge-pump current (Icp) and loop-filter components
(R, C) to facilitate reconfiguration of the PLL bandwidth
Figure 5–39 shows how you can dynamically adjust the PLL counter settings by
shifting their new settings into a serial shift-register chain or scan chain. Serial data is
input to the scan chain using the scandata port. Shift registers are clocked by scanclk.
The maximum scanclk frequency is 100 MHz. Serial data is shifted through the scan
chain as long as the scanclkena signal stays asserted. After the last bit of data is
clocked, asserting the configupdate signal for at least one scanclk clock cycle causes
the PLL configuration bits to be synchronously updated with the data in the scan
registers.
Figure 5–39. PLL Reconfiguration Scan Chain ⁽¹⁾
scandata
from m counter
from n counter
PFD
LF/K/CP (3)
VCO
scanclkena
configupdate
inclk
scandataout
/Ci (2)
/Ci-1
/C2
/C1
/C0
/m
/n
scandone
scanclk
Notes to Figure 5–39:
(1) Stratix IV left and right PLLs support C0 - C6 counters.
(2) i = 6 or i = 9.
(3) This figure shows the corresponding scan register for the K counter in between the scan registers for the charge pump and loop filter. The K
counter is physically located after the VCO.
1 The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, all counters are not updated simultaneously.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1