EP4SE360F35I4 Datasheet, PDF (275/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Figure 7–32. Stratix IV IOE Output and Output-Enable Path Registers ⁽¹⁾
From Core (2)
Half Data Rate to Single Data Rate Output-Enable Registers
DQ
DFF
0
1
From Core (2)
DQ
DQ
DFF
DFF
From Core
(wdata2) (2)
From Core
(wdata0) (2)
From Core
(wdata3) (2)
From Core
(wdata1) (2)
Half Data Rate to Single Data Rate Output Registers
DQ
DFF
DQ
DFF
0
1
D
Q
DFF
DQ
DFF
DQ
DFF
0
1
D
Q
DFF
DQ
DFF
D
Q
DFF
Alignment Registers (4)
DQ
DFF
Alignment Registers (4)
DQ
DFF
DQ
DFF
DQ
DFF
DQ
DFF
D
Q
DFF
DQ
DFF
Double Data Rate Output-Enable Registers
DFF
DQ
OE Reg A_OE
1
0
DFF
DQ
OR2
OE Reg BOE
Double Data Rate Output Registers
DFF
DQ
1
Output Reg Ao
0
DFF
DQ
TRI
DQ or DQS
Output Reg Bo
Half-Rate Clock (3)
Alignment
Clock (3)
Write
Clock (5)
Notes to Figure 7–32:
(1) You can bypass each register block of the output and output-enable paths.
(2) Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode.
(3) The half-rate clock comes from the PLL, while the alignment clock comes from the write-leveling delay chains.
(4) These registers are only used in DDR3 SDRAM interfaces for write-leveling purposes.
(5) The write clock can come from either the PLL or from the write-leveling delay chain. The DQ write clock and DQS write clock have a 90° offset between them.