EP4SE360F35I4 Datasheet, PDF (342/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–6
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Passive Parallel Configuration
Fast Passive Parallel Configuration
Fast passive parallel configuration in Stratix IV devices is designed to meet the
continuously increasing demand for faster configuration times. Stratix IV devices are
designed with the capability of receiving byte-wide configuration data per clock
cycle.
You can perform FPP configuration of Stratix IV devices using an intelligent host,
such as a MAX II device or a microprocessor.
FPP Configuration Using a MAX II Device as an External Host
FPP configuration using an external host provides the fastest method to configure
Stratix IV devices. In this configuration scheme, you can use a MAX II device as an
intelligent host that controls the transfer of configuration data from a storage device,
such as flash memory, to the target Stratix IV device. You can store configuration data
in .rbf, .hex, or .ttf format. When using the MAX II device as an intelligent host, a
design that controls the configuration process, such as fetching the data from flash
memory and sending it to the device, must be stored in the MAX II device.
1 If you are using the Stratix IV decompression and/or design security features, the
external host must be able to send a DCLK frequency that is ×4 the data rate.
The ×4 DCLK signal does not require an additional pin and is sent on the DCLK pin. The
maximum DCLK frequency is 125 MHz, which results in a maximum data rate of
250 Mbps. If you are not using the Stratix IV decompression or design security
features, the data rate is ×8 the DCLK frequency.
Figure 10–1 shows the configuration interface connections between the Stratix IV
device and a MAX II device for single device configuration.
Figure 10–1. Single Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
External Host
(MAX II Device or
Microprocessor)
V_CCPGM (1) V_CCPGM (1) V_CCPGM/V_CCIO (2)
10 kΩ
10 kΩ
10 kΩ
GND
Stratix IV Device
MSEL[2..0]
CONF_DONE
nSTATUS
nCE
nCEO
GND
N.C.
DATA[7..0]
nCONFIG
DCLK
Note to Figure 10–1:
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix IV device. V_CCPGM must be
high enough to meet the V_IH specification of the I/O on the device and the external host. Altera recommends powering
up all configuration system I/Os with V_CCPGM.
(2) A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when the external host is not driving
the line.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation