EP4SE360F35I4 Datasheet, PDF (366/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–30
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
1 If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 s to a maximum pulse width of 500 s, as defined in the t_STATUS specification.
In your system, you can have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied to GND,
while the nCEO pins are left floating. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLK and DATA lines are buffered for every fourth
device. Devices must be the same density and package. All devices start and complete
configuration at the same time.
Figure 10–12 shows multi-device PS configuration when both Stratix IV devices are
receiving the same configuration data.
Figure 10–12. Multiple-Device PS Configuration When Both Devices Receive the Same Data
Memory
ADDR
DATA0
V_{CCPGM (1)} V_{CCPGM (1) VCCPGM/VCCIO (2)}
10 k Ω 10 k Ω
10 kΩ
Stratix IV Device
Stratix IV Device
External Host
(MAX II Device or
Microprocessor)
GND
CONF_DONE
nSTATUS
nCE
nCEO
DATA0
nCONFIG
DCLK
MSEL2
MSEL1
MSEL0
N.C. (3)
V_CCPGM GND
CONF_DONE
nSTATUS
nCE
nCEO
DATA0
nCONFIG
DCLK
MSEL2
MSEL1
MSEL0
N.C. (3)
V_CCPGM
GND
GND
Notes to Figure 10–12:
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V_CCPGM must be high enough to
meet the V_IH specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V_CCPGM.
(2) A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when the external host is not driving the line.
(3) The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple devices.
You can use a single configuration chain to configure Stratix IV devices with other
Altera devices. To ensure that all devices in the chain complete configuration at the
same time, or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONE and nSTATUS pins must be tied together.
f For more information about configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in
volume 2 of the Configuration Handbook.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation