EP4SE360F35I4 Datasheet, PDF (106/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

4–26
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Four-Multiplier Adder
In the four-multiplier adder configuration shown in Figure 4–17, the DSP block can
implement two four-multiplier adders (one four-multiplier adder per half DSP block).
These modes are useful for implementing one-dimensional and two-dimensional
filtering applications. The four-multiplier adder is performed in two addition stages.
The outputs of two of the four multipliers are initially summed in the two first-stage
adder blocks. The results of these two adder blocks are then summed in the
second-stage adder block to produce the final four-multiplier adder result, as shown
by Equation 4–2 on page 4–5 and Equation 4–3 on page 4–5.
Figure 4–17. Four-Multiplier Adder Mode Shown for a Half DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
output_round
output_saturate
overflow (1)
dataa_0[ ]
datab_0[ ]
+
dataa_1[ ]
datab_1[ ]
dataa_2[ ]
+
result[ ]
datab_2[ ]
+
dataa_3[ ]
datab_3[ ]
Half-DSP Block
Note to Figure 4–17:
(1) Block output for accumulator overflow and saturate overflow.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation