EP4SE360F35I4 Datasheet, PDF (146/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–30
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Source-Synchronous Mode for LVDS Compensation
The goal of source-synchronous mode is to maintain the same data and clock timing
relationship seen at the pins of the internal serializer/deserializer (SERDES) capture
register, except that the clock is inverted (180° phase shift). Thus, source-synchronous
mode ideally compensates for the delay of the LVDS clock network plus any
difference in delay between these two paths:
■ Data pin-to-SERDES capture register
■ Clock input pin-to-SERDES capture register. In addition, the output counter must
provide the 180° phase shift
Figure 5–23 shows an example waveform of the clock and data in LVDS mode.
Figure 5–23. Phase Relationship Between the Clock and Data in LVDS Mode
Data pin
PLL
reference clock
at input pin
Data at register
Clock at register
No-Compensation Mode
In no-compensation mode, the PLL does not compensate for any clock networks. This
mode provides better jitter performance because the clock feedback into the PFD
passes through less circuitry. Both the PLL internal- and external-clock outputs are
phase-shifted with respect to the PLL clock input. Figure 5–24 shows an example
waveform of the PLL clocks’ phase relationship in no-compensation mode.
Figure 5–24. Phase Relationship Between the PLL Clocks in No Compensation Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port (1)
External PLL Clock Outputs (1)
Note to Figure 5–24:
(1) The PLL clock outputs lag the PLL input clocks depending on routine delays.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation