EP4SE360F35I4 Datasheet, PDF (320/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–40
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
Using Both Center Left and Right PLLs
You can use both center left and right PLLs to drive DPA-enabled channels
simultaneously, as long as they drive these channels in their adjacent banks only, as
shown in Figure 8–32.
If one of the center left and right PLLs drives the top and bottom banks, you cannot
use the other center left and right PLL to drive differential channels, as shown in
Figure 8–32.
If the top PLL_L2 and PLL_R2 drives DPA-enabled channels in the lower differential
bank, the PLL_L3 and PLL_R3 cannot drive DPA-enabled channels in the upper
differential banks and vice versa. In other words, the center left and right PLLs cannot
drive cross-banks simultaneously, as shown in Figure 8–33.
Figure 8–32. Center Left and Right PLLs Driving DPA-Enabled Differential I/Os
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Center
Left/Right PLL
(PLL_L2/PLL_R2)
Center
Left/Right PLL
(PLL_L3/PLL_R3)
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Center
Left/Right PLL
(PLL_L2/PLL_R2)
Center
Left/Right PLL
(PLL_L3/PLL_R3)
Unused
PLL
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation