EP4SE360F35I4 Datasheet, PDF (378/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–42
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Device Configuration Pins
Table 10–10 lists the dedicated configuration pins. You must connect these pins
properly on your board for successful configuration. Some of these pins may not be
required for your configuration schemes.
Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 1 of 4)
Pin Name
User Mode
Configuration
Scheme
VCCPGM
N/A
All
VCCPD
N/A
All
PORSEL
N/A
All
nIO_PULLUP
N/A
All
Pin Type
Power
Power
Input
Input
Description
Dedicated power pin. Use this pin to power all dedicated
configuration inputs, dedicated configuration outputs,
dedicated configuration bidirectional pins, and some of the
dual functional pins that are used for configuration.
You must connect this pin to 1.8, 2.5, or 3.0 V. V_CCPGM must
ramp-up from 0 V to V_CCPGM within 100 ms when PORSEL is
low or 4 ms when PORSEL is high. If V_CCPGM is not ramped
up within this specified time, your Stratix IV device will not
configure successfully. If your system does not allow a
V_CCPGM ramp-up within 100 ms or 4 ms, you must hold
nCONFIG low until all power supplies are stable.
Dedicated power pin. Use this pin to power the I/O
pre-drivers, JTAG input and output pins, and design
security circuitry.
You must connect this pin to 2.5 V or 3.0 V, depending on
the I/O standards selected. For the 3.0-V I/O standard,
V_CCPD = 3.0 V. For the 2.5 V or below I/O standards,
V_CCPD = 2.5 V.
V_CCPD must ramp-up from 0 V to 2.5 V / 3.0 V within
100 ms when PORSEL is low or 4 ms when PORSEL is high.
If V_CCPD is not ramped up within this specified time, your
Stratix IV device will not configure successfully. If your
system does not allow a V_CCPD to ramp-up time within
100 ms or 4 ms, you must hold nCONFIG low until all
power supplies are stable.
Dedicated input that selects between a standard POR time
or a fast POR time. A logic low selects a standard POR time
setting of 100 ms < T_POR < 300 ms and a logic high selects
a fast POR time setting of 4 ms < T_POR < 12 ms.
The PORSEL input buffer is powered by V_CC and has an
internal 5-kpull-down resistor that is always active. Tie
the PORSEL pin directly to V_CCPGM or GND.
Dedicated input that chooses whether the internal pull-up
resistors on the user I/O pins and dual-purpose I/O pins
(nCSO, nASDO, DATA[7..0], CLKUSR, and INIT_DONE) are
on or off before and during configuration. A logic high turns
off the weak internal pull-up resistors; a logic low turns
them on.
The nIO-PULLUP input buffer is powered by V_CC and has an
internal 5-k pull-down resistor that is always active. The
nIO-PULLUP can be tied directly to V_CCPGM, using a 1-k
pull-up resistor or tied directly to GND, depending on your
device requirements.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation