EP4SE360F35I4 Datasheet, PDF (160/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–44
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
■ After a switchover occurs, there may be a finite resynchronization period for the
PLL to lock onto a new clock. The exact amount of time it takes for the PLL to
re-lock depends on the PLL configuration.
■ The phase relationship between the input clock to the PLL and the output clock
from the PLL is important in your design. Assert areset for at least 10 ns after
performing a clock switchover. Wait for the locked signal to go high and be stable
before re-enabling the output clocks from the PLL.
■ Figure 5–38 shows how the VCO frequency gradually decreases when the current
clock is lost and then increases as the VCO locks on to the backup clock.
Figure 5–38. VCO Switchover Operating Frequency
Primary Clock Stops Running
ΔFvco
Switchover Occurs
VCO Tracks Secondary Clock
■ Disable the system during clock switchover if it is not tolerant of frequency
variations during the PLL resynchronization period. You can use the clkbad[0]
and clkbad[1] status signals to turn off the PFD (PFDENA = 0) so the VCO
maintains its most recent frequency. You can also use the state machine to switch
over to the secondary clock. When the PFD is re-enabled, output clock-enable
signals (clkena) can disable clock outputs during the switchover and
resynchronization period. When the lock indication is stable, the system can
re-enable the output clocks.
PLL Reconfiguration
PLLs use several divide counters and different VCO phase taps to perform frequency
synthesis and phase shifts. In Stratix IV PLLs, you can reconfigure both the counter
settings and phase-shift the PLL output clock in real time. You can also change the
charge pump and loop-filter components, which dynamically affects PLL bandwidth.
You can use these PLL components to update the output-clock frequency and PLL
bandwidth and to phase-shift in real time, without reconfiguring the entire Stratix IV
device.
The ability to reconfigure the PLL in real time is useful in applications that operate at
multiple frequencies. It is also useful in prototyping environments, allowing you to
sweep PLL output frequencies and adjust the output-clock phase dynamically. For
instance, a system generating test patterns is required to generate and transmit
patterns at 75 or 150 MHz, depending on the requirements of the device under test.
Reconfiguring the PLL components in real time allows you to switch between two
such output frequencies within a few microseconds. You can also use this feature to
adjust clock-to-out (tCO) delays in real time by changing the PLL output clock phase
shift. This approach eliminates the need to regenerate a configuration file with the
new PLL settings.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation