EP4SE360F35I4 Datasheet, PDF (151/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
5–35
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with a variable
duty cycle. This feature is supported on the PLL post-scale counters. The duty-cycle
setting is achieved by a low and high time-count setting for the post-scale counters. To
determine duty cycle choices, the Quartus II software uses the frequency input and
the required multiply or divide rate. The post-scale counter value determines the
precision of the duty cycle. Precision is defined as 50% divided by the post-scale
counter value. For example, if the C0 counter is 10, steps of 5% are possible for
duty-cycle choices from 5% to 90%.
If the PLL is in external feedback mode, set the duty cycle for the counter driving the
fbin pin to 50%. Combining the programmable duty cycle with programmable phase
shift allows the generation of precise non-overlapping clocks.
Programmable Phase Shift
Use phase shift to implement a robust solution for clock delays in Stratix IV devices.
Implement phase shift by using a combination of the VCO phase output and the
counter starting time. A combination of VCO phase output and counter starting time
is the most accurate method of inserting delays because it is only based on counter
settings, which are independent of process, voltage, and temperature (PVT).
You can phase-shift the output clocks from the Stratix IV PLLs in either of these two
resolutions:
■ Fine resolution using VCO phase taps
■ Coarse resolution using counter starting time
Implement fine-resolution phase shifts by allowing any of the output counters
(C[n..0]) or the m counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution. Equation 5–1
shows the minimum delay time that you can insert using this method.
Equation 5–1. Fine-Resolution Phase Shift
Φ_fine =
1
8
T_VCO
=
1
8f_VCO
=
N
8Mf_REF
where f_REF is the input reference clock frequency.
For example, if f_REF is 100 MHz, N is 1, and M is 8, then f_VCO is 800 MHz and  _fine
equals 156.25 ps. This phase shift is defined by the PLL operating frequency, which is
governed by the reference clock frequency and the counter settings.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1