EP4SE360F35I4 Datasheet, PDF (274/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–50
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
There are three registers in the DDR input registers block. Two registers capture data
on the positive and negative edges of the clock, while the third register aligns the
captured data. You can choose to use the same clock for the positive edge and
negative edge registers, or two complementary clocks (DQS/CQ for the positive-edge
register and DQSn/CQn for the negative-edge register). The third register that aligns
the captured data uses the same clock as the positive edge registers.
The resynchronization registers consist of up to three levels of registers to
resynchronize the data to the system clock domain. These registers are clocked by the
resynchronization clock that is either generated by the PLL or the read-leveling delay
chain. The outputs of the resynchronization registers can go straight to the core or to
the HDR blocks, which are clocked by the divided-down resynchronization clock.
For more information about the read-leveling delay chain, refer to “Leveling
Circuitry” on page 7–46.
Figure 7–32 shows the registers available in the Stratix IV output and output-enable
paths. The path is divided into the HDR block, resynchronization registers, and
output and output-enable registers. The device can bypass each block of the output
and output-enable path.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation