EP4SE360F35I4 Datasheet, PDF (206/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

6–32
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
OCT Calibration
Stratix IV devices support calibrated on-chip series termination (R_S) and calibrated
on-chip parallel termination (R_T) on all I/O pins. You can calibrate the device’s I/O
bank with any of the OCT calibration blocks available in the device provided the
V_CCIO of the I/O bank with the pins using calibrated OCT matches the V_CCIO of the
I/O bank with the calibration block and its associated RUP and RDN pins.
OCT Calibration Block Location
Table 6–10 and Table 6–11 list the location of OCT calibration blocks in Stratix IV
devices. For both tables, the following legend applies:
■ “Y” indicates I/O banks with OCT calibration block
■ ”N” indicates I/O banks without OCT calibration block
■ “—” indicates I/O banks that are not available in the device
1 Table 6–10 and Table 6–11 do not show transceiver banks and transceiver calibration
blocks.
Table 6–10 lists the OCT calibration blocks in Banks 1A through 4C.
Table 6–10. OCT Calibration Block Counts and Placement in Stratix IV Devices (1A through 4C) (Part 1 of 2)
Device
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
Pin
780
780
1152
1152
1517
1760
1152
1517
1760
780
780
1152
780
1152
1517
780
1152
1517
Number of
Bank
OCT Blocks _{1A 1B 1C 2A 2B 2C 3A 3B 3C 4A 4B 4C}
8
Y—N Y—N Y—N Y—N
8
Y—N Y—N Y—N Y—N
8
Y—N Y—N Y N N Y N N
8
Y—N Y—N Y N N Y N N
10
YNNYNNYNYYNN
10
YNNYNNYNYYNN
8
Y—N Y—N Y N N Y N N
10
YNNYNNYNYYNN
10
YNNYNNYNYYNN
8
Y—N Y—N Y—N Y—N
8
Y—N Y—N Y—N Y—N
8
Y — N ——— Y — N Y — N
8
Y—N Y—N Y—N Y—N
8
Y — N ——— Y N N Y N N
8
Y—N Y—N Y N N Y N N
8
Y—N Y—N Y—N Y—N
8
Y — N ——— Y N N Y N N
8
Y—N Y—N Y N N Y N N
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation