EP4SE360F35I4 Datasheet, PDF (156/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–40
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Stratix IV PLLs support a fully configurable clock switchover capability. Figure 5–34
shows a block diagram of the automatic switchover circuit built into the PLL. When
the current reference clock is not present, the clock sense block automatically switches
to the backup clock for PLL reference. The clock switchover circuit also sends out
three status signals—clkbad[0], clkbad[1], and activeclock—from the PLL to
implement a custom switchover circuit in the logic array. You can select a clock source
as the backup clock by connecting it to the inclk1 port of the PLL in your design.
Figure 5–34. Automatic Clock Switchover Circuit Block Diagram
clkbad[0]
clkbad[1]
activeclock
inclk0
inclk1
Clock
Sense
clksw
Switchover
State
Machine
Clock Switch
Control Logic
clkswitch
muxout
n Counter
refclk
PFD
fbclk
Automatic Clock Switchover
Use the switchover circuitry to automatically switch between inclk0 and inclk1
when the current reference clock to the PLL stops toggling. For example, in
applications that require a redundant clock with the same frequency as the reference
clock, the switchover state machine generates a signal (clksw) that controls the
multiplexer select input, as shown in Figure 5–34. In this case, inclk1 becomes the
reference clock for the PLL. When using automatic switchover mode, you can switch
back and forth between inclk0 and inclk1 any number of times when one of the two
clocks fails and the other clock is available.
When using automatic clock switchover mode, the following requirements must be
satisfied:
■ Both clock inputs must be running
■ The period of the two clock inputs can differ by no more than 100% (2×)
If the current clock input stops toggling while the other clock is also not toggling,
switchover is not initiated and the clkbad[0..1] signals are not valid. Also, if both
clock inputs are not the same frequency, but their period difference is within 100%, the
clock sense block detects when a clock stops toggling, but the PLL may lose lock after
the switchover is completed and needs time to re-lock.
1 Altera recommends resetting the PLL using the areset signal to maintain the phase
relationships between the PLL input and output clocks when using clock switchover.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation