EP4SE360F35I4 Datasheet, PDF (200/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

6–26
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
On-Chip Series Termination with Calibration
Stratix IV devices support on-chip series termination with calibration in all banks. The
on-chip series termination calibration circuit compares the total impedance of the I/O
buffer to the external 25- ±1% or 50- ±1% resistors connected to the RUP and RDN
pins and dynamically enables or disables the transistors until they match.
The R_S shown in Figure 6–19 is the intrinsic impedance of the transistors. Calibration
occurs at the end of device configuration. When the calibration circuit finds the
correct impedance, it powers down and stops changing the characteristics of the
drivers.
Figure 6–19. On-Chip Series Termination with Calibration
Stratix IV Driver
Series Termination
V_CCIO
Receiving
Device
R_S
Z_O = 50 Ω
R_S
GND
Table 6–6 lists the I/O standards that support on-chip series termination with and
without calibration.
Table 6–6. Selectable I/O Standards for On-Chip Series Termination with and Without Calibration
(Part 1 of 2)
I/O Standard
3.3-V LVTTL/LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
On-Chip Series Termination Setting
Row I/O ()
50
25
50
25
50
25
50
50
50
25
50
25
Column I/O ()
50
25
50
25
50
25
50
25
50
25
50
25
50
25
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation