EP4SE360F35I4 Datasheet, PDF (53/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
2–17
Register Chain
In addition to general routing outputs, ALMs in the LAB have register-chain outputs.
Register-chain routing allows registers in the same LAB to be cascaded together. The
register-chain interconnect allows the LAB to use LUTs for a single combinational
function and the registers to be used for an unrelated shift-register implementation.
These resources speed up connections between ALMs while saving local interconnect
resources (refer to Figure 2–14). The Quartus II Compiler automatically takes
advantage of these resources to improve utilization and performance.
Figure 2–14. Register Chain within the LAB ⁽¹⁾
Combinational
Logic
adder0
adder1
reg_chain_in
From previous ALM
within the LAB
labclk
To general or
local routing
DQ
To general or
local routing
reg0
DQ
reg1
To general or
local routing
To general or
local routing
Combinational
Logic
adder0
adder1
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
reg_chain_out
To next ALM
within the LAB
Note to Figure 2–14:
(1) You can use the combinational or adder logic to implement an unrelated, un-registered function.
For more information about the register chain interconnect, refer to “ALM
Interconnects” on page 2–18.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1