EP4SE360F35I4 Datasheet, PDF (346/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–10
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Passive Parallel Configuration
Figure 10–2 shows how to configure multiple Stratix IV devices using a MAX II
device. This circuit is similar to the FPP configuration circuit for a single device,
except the devices are cascaded for multi-device configuration.
Figure 10–2. Multi-Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
External Host
(MAX II Device or
Microprocessor)
VCCPGM (1) VCCPGM (1) V_CCPGM/V_CCIO (2)
10 kΩ
10 kΩ
10 kΩ
GND
Stratix IV Device 1
MSEL[2..0]
CONF_DONE
nSTATUS
GND
nCE
nCEO
DATA[7..0]
nCONFIG
DCLK
Stratix IV Device 2
MSEL[2..0]
CONF_DONE
nSTATUS
nCE
nCEO
GND
N.C.
DATA[7..0]
nCONFIG
DCLK
Note to Figure 10–2:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V_CCPGM must be high enough
to meet the V_IH specification of the I/O standard on the device and the external host. Altera recommends powering up all configuration system
I/Os with V_CCPGM.
(2) A pull-up or pull-down resistor helps keep the nCONFIG line in a known state when the external host is not driving the line.
In a multi-device FPP configuration, the first device’s nCE pin is connected to GND
while its nCEO pin is connected to nCE of the next device in the chain. The last device’s
nCE input comes from the previous device, while its nCEO pin is left floating. After the
first device completes configuration in a multi-device configuration chain, its nCEO pin
drives low to activate the second device’s nCE pin, which prompts the second device
to begin configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent to the
MAX II device. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. The configuration signals may
require buffering to ensure signal integrity and prevent clock skew problems. Ensure
that the DCLK and DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user mode at the same
time.
All nSTATUS and CONF_DONE pins are tied together; if any device detects an error,
configuration stops for the entire chain and you must reconfigure the entire chain. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUS pin low. This behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the devices release
their nSTATUS pins after a reset time-out period (a maximum of 500 s). After all
nSTATUS pins are released and pulled high, the MAX II device tries to reconfigure the
chain without pulsing nCONFIG low. If this option is turned off, the MAX II device
must generate a low-to-high transition (with a low pulse of at least 2 s) on nCONFIG to
restart the configuration process.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation