EP4SE360F35I4 Datasheet, PDF (411/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 11: SEU Mitigation in Stratix IV Devices
Error Detection Pin Description
11–5
1 After the test completes, Altera recommends reconfiguring the device.
Automated Single-Event Upset Detection
Stratix IV devices offer on-chip circuitry for automated checking of SEU detection.
Some applications that require the device to operate error-free in high-neutron flux
environments require periodic checks to ensure continued data integrity. The error
detection CRC feature ensures data reliability and is one of the best options for
mitigating SEU.
You can implement the error detection CRC feature with existing circuitry in
Stratix IV devices, eliminating the need for external logic. The CRC_ERROR pin reports a
soft error when the configuration CRAM data is corrupted. You must decide whether
to reconfigure the device or to ignore the error.
Error Detection Pin Description
Depending on the type of error detection feature you choose, you must use different
error detection pins to monitor the data during user mode.
CRC_ERROR Pin
Table 11–3 describes the CRC_ERROR pin.
Table 11–3. CRC_ERROR Pin Description
Pin Name
CRC_ERROR
Pin Type
I/O and
open-drain
Description
Active-high signal indicates that the error detection circuit has detected errors in the
configuration CRAM bits. This pin is optional and is used when the error detection CRC
circuit is enabled. When the error detection CRC circuit is disabled, it is a user I/O pin.
To use the CRC_ERROR pin, you can either tie this pin to V_CCPGM through a 10k resistor or,
depending on the input voltage specification of the system receiving the signal, you can tie
this pin to a different pull-up voltage.
1 The WYSIWYG function performs optimization on the Verilog Quartus Mapping
(VQM) netlist within the Quartus II software.
f For more information about the stratixiv_crcblock WYSIWYG function, refer to the
AN 539: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA
Devices.
f For more information about the CRC_ERROR pin for Stratix IV devices, refer to Device
Pin-Outs on the Altera website.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1