EP4SE360F35I4 Datasheet, PDF (158/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–42
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Figure 5–36 shows a clock switchover waveform controlled by clkswitch. In this case,
both clock sources are functional and inclk0 is selected as the reference clock;
clkswitch goes high, which starts the switchover sequence. On the falling edge of
inclk0, the counter’s reference clock, muxout, is gated off to prevent clock glitching.
On the falling edge of inclk1, the reference clock multiplexer switches from inclk0 to
inclk1 as the PLL reference and the activeclock signal changes to indicate which
clock is currently feeding the PLL.
Figure 5–36. Clock Switchover Using the clkswitch (Manual) Control ⁽¹⁾
inclk0
inclk1
muxout
clkswitch
activeclock
clkbad0
clkbad1
Note to Figure 5–36:
(1) To initiate a manual clock switchover event, both inclk0 and inclk1 must be running when the clkswitch signal
goes high.
In automatic override with manual switchover mode, the activeclock signal mirrors
the clkswitch signal. As both clocks are still functional during the manual switch,
neither clkbad signal goes high. Because the switchover circuit is positive-edge
sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch
back from inclk1 to inclk0. When the clkswitch signal goes high again, the process
repeats. clkswitch and automatic switch only work if the clock being switched to is
available. If the clock is not available, the state machine waits until the clock is
available.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation