EP4SE360F35I4 Datasheet, PDF (18/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

1–4
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
Stratix IV E Device
Stratix IV E devices provide an excellent solution for applications that do not require
high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive.
Figure 1–2 shows a high-level Stratix IV E chip view.
Figure 1–2. Stratix IV E Chip View ⁽¹⁾
General Purpose
General Purpose
I/O and Memory ^{PLL PLL} I/O and Memory
Interface
Interface
PLL
PLL
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
PLL
PLL
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
PLL
PLL
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
PLL
PLL
General Purpose
General Purpose
I/O and Memory ^{PLL PLL} I/O and Memory
Interface
Interface
General Purpose I/O and
High-Speed LVDS I/O with DPA
and Soft-CDR
General Purpose I/O and
150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
Note to Figure 1–2:
(1) Resource counts vary with device selection, package selection, or both.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation