EP4SE360F35I4 Datasheet, PDF (137/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
5–21
Table 5–8. PLL Features in Stratix IV Devices (Part 2 of 2) ⁽¹⁾
Feature
Clock input pins ⁽²⁾
External feedback input pin
Spread-spectrum input clock tracking
PLL cascading
Stratix IV Top/Bottom PLLs
Stratix IV Left/Right PLLs
4 single-ended or 4 differential pin pairs
4 single-ended or 4 differential pin
pairs
Single-ended or differential
Single-ended only
Yes ⁽³⁾
Yes ⁽³⁾
Through GCLK and RCLK and a dedicated
path between adjacent PLLs
Through GCLK and RCLK and
dedicated path between adjacent PLLs
(4)
Compensation modes
PLL drives LVDSCLK and LOADEN
VCO output drives the DPA clock
Phase shift resolution
Programmable duty cycle
Output counter cascading
Input clock switchover
All except LVDS clock network
compensation
No
No
Down to 96.125 ps ⁽⁵⁾
Yes
Yes
Yes
All except external feedback mode
when using differential I/Os
Yes
Yes
Down to 96.125 ps ⁽⁵⁾
Yes
Yes
Yes
Notes to Table 5–8:
(1) While there is pin compatibility, there is no hard IP block placement compatibility.
(2) General purpose I/O pins cannot drive the PLL clock input pins.
(3) Provided input clock jitter is within input jitter tolerance specifications.
(4) The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs.
(5) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Stratix IV
device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and
divide parameters.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1