EP4SE360F35I4 Datasheet, PDF (195/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–21
Table 6–3. Programmable Current Strength (Part 2 of 2) ⁽¹⁾, ⁽²⁾
I/O Standard
I_OH / I_OL Current Strength
Setting (mA) for
Column I/O Pins
I_OH / I_OL Current Strength
Setting (mA) for
Row I/O Pins
HSTL-12 Class I
12, 10, 8, 6, 4
8, 6, 4
HSTL-12 Class II
16
—
Notes to Table 6–3:
(1) The default setting in the Quartus II software is 50-OCT R_S without calibration for all non-voltage reference and
HSTL and SSTL Class I I/O standards. The default setting is 25-OCT R_S without calibration for HSTL and SSTL
Class II I/O standards.
(2) The 3.3-V LVTTL and 3.3-V LVCMOS are supported using V_CCIO and V_CCPD at 3.0 V.
1 Altera recommends performing IBIS or SPICE simulations to determine the best
current strength setting for your specific application.
Programmable Slew Rate Control
The output buffer for each Stratix IV device regular- and dual-function I/O pin has a
programmable output slew-rate control that you can configure for low-noise or
high-speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. A slower slew rate can help reduce system noise, but adds
a nominal delay to the rising and falling edges. Each I/O pin has an individual
slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis.
1 You cannot use the programmable slew rate feature when using OCT.
The Quartus II software allows four settings for programmable slew rate control—0,
1, 2, and 3—where 0 is slow slew rate and 3 is fast slew rate. Figure 6–4 lists the
default slew rate settings from the Quartus II software.
Table 6–4. Default Slew Rate Settings
I/O Standard
1.2-V, 1.5-V, 1.8-V, 2.5-V LVCMOS, and 3.3-V LVTTL/LVCMOS
SSTL-2, SSTL-18, SSTL-15, HSTL-18, HSTL-15, and HSTL-12
3.0-V PCI/PCI-X
LVDS_E_1R, mini-LVDS_E_1R, and RSDS_E_1R
LVDS_E_3R, mini-LVDS_E_3R, and RSDS_E_3R
Slew Rate Option
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
Default Slew Rate
3
3
3
3
3
You can use faster slew rates to improve the available timing margin in
memory-interface applications or when the output pin has high-capacitive loading.
1 Altera recommends performing IBIS or SPICE simulations to determine the best slew
rate setting for your specific application.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1