EP4SE360F35I4 Datasheet, PDF (38/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

2–2
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Logic Array Blocks
Figure 2–1 shows the Stratix IV LAB structure and interconnects.
Figure 2–1. Stratix IV LAB Structure and Interconnects
C4 C12
Row Interconnects of
Variable Speed & Length
R20
R4
Direct link
interconnect from
adjacent block
ALMs
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Direct link
interconnect to
adjacent block
Local Interconnect _LAB
MLAB
Local Interconnect is Driven
from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
The LAB of the Stratix IV device has a derivative called memory LAB (MLAB), which
adds look-up table (LUT)-based SRAM capability to the LAB, as shown in Figure 2–2.
The MLAB supports a maximum of 640 bits of simple dual-port static random access
memory (SRAM). You can configure each ALM in an MLAB as either a 64 × 1 or a
32 × 2 block, resulting in a configuration of either a 64 × 10 or a 32 × 20 simple
dual-port SRAM block. MLAB and LAB blocks always coexist as pairs in all Stratix IV
families. MLAB is a superset of the LAB and includes all LAB features.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation