EP4SE360F35I4 Datasheet, PDF (218/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

6–44
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Differential LVPECL
In Stratix IV devices, the LVPECL I/O standard is supported on input clock pins on
column and row I/O banks. LVPECL output operation is not supported in Stratix IV
devices. LVDS input buffers are used to support LVPECL input operation. AC
coupling is required when the LVPECL common-mode voltage of the output buffer is
higher than the LVPECL input common-mode voltage. Figure 6–32 shows the
AC-coupled termination scheme. The 50- resistors used at the receiver end are
external to the device.
Figure 6–32. LVPECL AC-Coupled Termination ⁽¹⁾
Altera FPGA
LVPECL Output Buffer
Stratix IV LVPECL
Input Buffer
0.1 μF
0.1 μF
Z_O= 50 Ω
Z_{O= 50 Ω}
V_ICM
50 Ω
50 Ω
Note to Figure 6–32:
(1) The LVPECL AC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
DC-coupled LVPECL is supported if the LVPECL output common mode voltage is
within the Stratix IV LVPECL input buffer specification (Figure 6–33).
Figure 6–33. LVPECL DC-Coupled Termination ⁽¹⁾
Altera FPGA
LVPECL Output Buffer
Stratix IV LVPECL
Input Buffer
Z_O = 50 Ω
Z_O = 50 Ω
100 Ω
Note to Figure 6–33:
(1) The LVPECL DC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation