EP4SE360F35I4 Datasheet, PDF (413/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 11: SEU Mitigation in Stratix IV Devices
Error Detection Block
11–7
Error Detection Registers
There is one set of 16-bit registers in the error detection circuitry that stores the
computed CRC signature. A non-zero value on the syndrome register causes the
CRC_ERROR pin to be set high.
Figure 11–1 shows the error detection circuitry, syndrome registers, and error injection
block.
Figure 11–1. Error Detection Block Diagram
Readback bit
stream with
expected CRC
included
Error Detection
State Machine
Control Signals
16-Bit CRC
Calculation and Error
Search Engine
8
30
Error Message
Register
Error Injection Block
Fault Injection
Register
JTAG Fault
Injection Register
JTAG Update
Register
46
User Update
Register
JTAG Shift
Register
User Shift
Register
Syndrome
Register
16
CRC_ERROR
JTAG TDO
General Routing
Table 11–4 lists the registers shown in Figure 11–1.
Table 11–4. Error Detection Registers (Part 1 of 2)
Register
Syndrome Register
Error Message
Register
Description
This register contains the CRC signature of the current frame through the error detection
verification cycle. The CRC_ERROR signal is derived from the contents of this register.
This 46-bit register contains information on the error type, location of the error, and the actual
syndrome. The types of errors and location reported are single- and double-adjacent bit errors.
The location bits for other types of errors are not identified by the error message register. The
content of the register can be shifted out through the SHIFT_EDERROR_REG JTAG instruction or to
the core through the core interface.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1