EP4SE360F35I4 Datasheet, PDF(257/432 Page) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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EP4SE360F35I4 Datasheet, PDF (257/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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Chapter 7: External Memory Interfaces in Stratix IV Devices

Stratix IV External Memory Interface Features

7â33

1 You can only have one memory interface in each I/O sub-bank (such as I/O

sub-banks 1A, 1B, and 1C) when you use leveling delay chains. This is because there

is only one leveling delay chain per I/O sub-bank.

Table 7â4. DLL Location and Supported I/O Banks

DLL

Location

Accessible I/O Banks (1)

DLL0

DLL1

DLL2

DLL3

Top-left corner

Bottom-left corner

Bottom-right corner

Top-right corner

1A, 1B, 1C, 2A, 2B, 2C, 7A, 7B, 7C, 8A, 8B, 8C

1A, 1B, 1C, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C

3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C

5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C

Note to Table 7â4:

(1) The DLL can access these I/O banks if they are available for memory interfacing.

The reference clock for each DLL may come from PLL output clocks or any of the two

dedicated clock input pins located in either side of the DLL. Table 7â5 through

Table 7â17 lists the available DLL reference clock input resources for the Stratix IV

device family.

1 When you have a dedicated PLL that only generates the DLL input reference clock, set

the PLL mode to No Compensation to achieve better performance or the Quartus II

software changes it automatically. Because the PLL does not use any other outputs, it

does not need to compensate for any clock paths.

Table 7â5. DLL Reference Clock Input for EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin

FineLine BGA Package

DLL

DLL0

DLL1

DLL2

DLL3

CLKIN

(Top/Bottom)

CLK12P

CLK13P

CLK14P

CLK15P

CLK4P

CLK5P

CLK6P

CLK7P

CLK4P

CLK5P

CLK6P

CLK7P

CLK12P

CLK13P

CLK14P

CLK15P

CLKIN

(Left/Right)

CLK0P

CLK1P

CLK2P

CLK3P

CLK0P

CLK1P

CLK2P

CLK3P

â

PLL

(Top/Bottom)

PLL

(Left/Right)

PLL_T1

PLL_L2

PLL_B1

â

PLL_B1

â

PLL

(Corner)

â

PLL_T1

â

February 2011 Altera Corporation

Stratix IV Device Handbook

Volume 1

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