EP4SE360F35I4 Datasheet, PDF(145/432 Page) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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EP4SE360F35I4 Datasheet, PDF (145/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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Chapter 5: Clock Networks and PLLs in Stratix IV Devices

PLLs in Stratix IV Devices

5â29

Source Synchronous Mode

If data and clock arrive at the same time on the input pins, the same phase

relationship is maintained at the clock and data ports of any IOE input register.

Figure 5â22 shows an example waveform of the clock and data in this mode. Altera

recommends source synchronous mode for source-synchronous data transfers. Data

and clock signals at the IOE experience similar buffer delays as long as you use the

same I/O standard.

Figure 5â22. Phase Relationship Between Clock and Data in Source-Synchronous Mode

Data pin

PLL

reference clock

at input pin

Data at register

Clock at register

Source-synchronous mode compensates for the delay of the clock network used plus

any difference in the delay between these two paths:

â Data pin to the IOE register input

â Clock input pin to the PLL PFD input

The Stratix IV PLL can compensate multiple pad-to-input-register paths, such as a

data bus when it is set to use source-synchronous compensation mode. You can use

the âPLL Compensationâ assignment in the Quartus II software Assignment Editor to

select which input pins are used as the PLL compensation targets. You can include

your entire data bus, provided the input registers are clocked by the same output of a

source-synchronous-compensated PLL. In order for the clock delay to be properly

compensated, all of the input pins must be on the same side of the device. The PLL

compensates for the input pin with the longest pad-to-register delay among all input

pins in the compensated bus.

If you do not make the âPLL Compensationâ assignment, the Quartus II software

automatically selects all of the pins driven by the compensated output of the PLL as

the compensation target.

September 2012 Altera Corporation

Stratix IV Device Handbook

Volume 1

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