EP4SE360F35I4 Datasheet, PDF (113/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–33
Two saturation modes are supported in Stratix IV:
■ Asymmetric saturation mode
■ Symmetric saturation mode
1 You must select one of the two options at compile time.
In 2’s-complement format, the maximum negative number that can be represented is
–2^(n–1), while the maximum positive number is 2^(n–1) – 1. Symmetrical saturation limits
the maximum negative number to –2^(n–1) + 1. For example, for 32 bits:
■ Asymmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000000
■ Symmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000001
Table 4–8 lists how saturation works. In this example, a 44-bit input is saturated to
36-bits.
Table 4–8. Examples of Saturation
44- to 36-Bits Saturation
5926AC01342h
ADA38D2210h
Symmetric SAT Result
7FFFFFFFFh
800000001h
Asymmetric SAT Result
7FFFFFFFFh
800000000h
Stratix IV devices have up to 16 configurable bit positions out of the 44-bit bus
([43:0]) for the rounding and saturate logic unit, providing higher flexibility. These
16-bit positions are located at bits [21:6] for rounding and [43:28] for saturation, as
shown in Figure 4–21.
1 You must select the 16 configurable bit positions at compile time.
Figure 4–21. Rounding and Saturation Locations
16 User defined SAT Positions (bit 43-28)
43 42
29 28
10
16 User defined RND Positions (bit 21-6)
43 42
21 20
76
0
1 For symmetric saturation, the RND bit position is also used to determine where the
LSP for the saturated data is located.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1