EP4SE360F35I4 Datasheet, PDF (261/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–37
Table 7–12. DLL Reference Clock Input for EP4SE530 and EP4SE820 Devices in the 1517- and 1760-Pin FineLine BGA
Packages
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
DLL1
DLL2
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
CLK12P
CLK13P
CLK14P
CLK15P
CLK0P
CLK1P
CLK2P
CLK3P
CLK0P
CLK1P
CLK2P
CLK3P
CLK8P
CLK9P
CLK10P
CLK11P
CLK8P
CLK9P
CLK10P
CLK11P
PLL_T1
PLL_L2
PLL_L1
PLL_B1
PLL_L3
PLL_L4
PLL_B2
PLL_R3
PLL_R4
PLL_T2
PLL_R2
PLL_R1
Table 7–13. DLL Reference Clock Input for EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1517-Pin FineLine BGA Package
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN
(Top/Bottom)
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
CLK12P
CLK13P
CLK14P
CLK15P
CLKIN
(Left/Right)
CLK0P
CLK1P
CLK2P
CLK3P
CLK0P
CLK1P
CLK2P
CLK3P
CLK8P
CLK9P
CLK10P
CLK11P
CLK8P
CLK9P
CLK10P
CLK11P
PLL
(Top/Bottom)
PLL_T1
PLL
(Left/Right)
PLL_L2
PLL_B1
PLL_L3
PLL_B2
PLL_R3
PLL_T2
PLL_R2
PLL
(Corner)
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February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1