EP4SE360F35I4 Datasheet, PDF (250/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–26
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Using the R_UP and R_DN Pins in a DQS/DQ Group Used for Memory Interfaces
You can use the DQS/DQSn pins in some of the ×4 groups as R_UP and R_DN pins (listed
in the pin table). You cannot use a ×4 DQS/DQ group for memory interfaces if any of
its pin members are used as R_UP and R_DN pins for OCT calibration. You may be able to
use the ×8/×9 group that includes this ×4 DQS/DQ group, if either of the following
applies:
■ You are not using DM pins with your differential DQS pins
■ You are not using complementary or differential DQS pins
You can use the ×8/×9 group because a DQS/DQ ×8/×9 group actually comprises 12
pins, as the groups are formed by stitching two DQS/DQ groups in ×4 mode with six
pins each (refer to Table 7–1 on page 7–5). A typical ×8 memory interface consists of
one DQS, one DM, and eight DQ pins that add up to 10 pins. If you choose your pin
assignment carefully, you can use the two extra pins for R_UP and R_DN. In a DDR3
SDRAM interface, you must use differential DQS, which means that you only have
one extra pin. In this case, pick different pin locations for the R_UP and R_DN pins (for
example, in the bank that contains the address and command pins).
You cannot use the R_UP and R_DN pins shared with DQS/DQ group pins when using
×9 QDR II+/QDR II SRAM devices, as the R_UP and R_DN pins are dual purpose with
the CQn pins. In this case, pick different pin locations for R_UP and R_DN pins to avoid
conflict with memory interface pin placement. In this case, you have the choice of
placing the R_UP and R_DN pins in the data-write group or in the same bank as the
address and command pins.
There is no restriction on using ×16/×18 or ×32/×36 DQS/DQ groups that include the
×4 groups whose pins are being used as R_UP and R_DN pins, because there are enough
extra pins that can be used as DQS pins.
1 For ×8, ×16/×18, or ×32/×36 DQS/DQ groups whose members are used for R_UP and
R_DN, you must assign DQS and DQ pins manually. The Quartus^® II software might
not be able to place DQS and DQ pins without manual pin assignments, resulting in a
“no-fit”.
Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface
This implementation combines ×16/×18 DQS/DQ groups to interface with a ×36
QDR II+/QDR II SRAM device. The ×36 read data bus uses two ×16/×18 groups
while the ×36 write data uses another two ×16/×18 or four ×8/×9 groups. The
CQ/CQn signal traces are split on the board trace to connect to two pairs of CQ/CQn
pins in the FPGA. This is the only connection on the board that you need to change for
this implementation. Other QDR II+/QDR II SRAM interface rules for Stratix IV
devices also apply for this implementation.
1 The ALTMEMPHY megafunction and UniPHY-based external memory interface IPs
do not use the QVLD signal, so you can leave the QVLD signal unconnected as in any
QDR II+/QDR II SRAM interface.
f For more information about the ALTMEMPHY megafunction or UniPHY-based IPs,
refer to the External Memory Interface Handbook.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation