EP4SE360F35I4 Datasheet, PDF (317/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
8–37
4. Select the LVDS receiver serial input ports (from the list) according to the input
delay you set. Click OK.
5. In the Set Input Delay window, set the appropriate values in the Input Delay
Options section and Delay value.
6. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
7. Assign the appropriate delay for all the LVDS receiver input ports following these
steps. If you have already assigned Input Delay and you need to add more delay
to that input port, use the Add Delay option in the Set Input Delay window.
1 If no input delay is set in the TimeQuest Timing Analyzer, the receiver
channel-to-channel skew (RCCS) defaults to zero. You can also directly set the input
delay in a Synopsys Design Constraint file (.sdc) using the set_input_delay
command.
f For more information about .sdc commands and the TimeQuest Timing Analyzer,
refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II
Development Software Handbook.
Example 8–2 shows the RSKM calculation.
Example 8–2. RSKM
Data Rate: 1 Gbps, Board channel-to-channel skew = 200 ps
For Stratix IV devices:
TCCS = 100 ps (pending characterization)
SW = 300 ps (pending characterization)
TUI = 1000 ps
Total RCCS = TCCS + Board channel-to-channel skew= 100 ps + 200 ps
= 300 ps
RSKM= TUI - SW - RCCS
= 1000 ps - 300 ps - 300 ps
= 400 ps > 0
Because the RSKM > 0 ps, receiver non-DPA mode must work correctly.
1 You can also calculate RSKM using the steps described in “Guidelines for DPA-
Enabled Differential Channels” on page 8–38.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1