EP4SE360F35I4 Datasheet, PDF (333/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 9: Hot Socketing and Power-On Reset in Stratix IV Devices
9–3
Hot-Socketing Feature Implementation in Stratix IV Devices
Hot-Socketing Feature Implementation in Stratix IV Devices
The hot-socketing feature turns off the output buffer during power up and power
down of the V_CC, V_CCAUX, V_CCIO, V_CCPGM, or V_CCPD power supplies. The hot-socketing
circuitry generates an internal HOTSCKT signal when the V_CC, V_CCAUX, V_CCIO, V_CCPGM,
or V_CCPD power supplies are below the threshold voltage. Hot-socketing circuitry is
designed to prevent excess I/O leakage during power up. When the voltage ramps up
very slowly, it is still relatively low, even after the POR signal is released and the
configuration is completed. The CONF_DONE, nCEO, and nSTATUS pins fail to respond, as
the output buffer cannot flip from the state set by the hot-socketing circuit at this low
voltage. Therefore, the hot-socketing circuitry has been removed from these
configuration pins to make sure that they are able to operate during configuration.
Thus, it is expected behavior for these pins to drive out during power-up and
power-down sequences.
Figure 9–1 shows the Stratix IV device’s I/O pin circuitry.
Figure 9–1. Hot-Socketing Circuitry for Stratix IV Devices
V_CCIO
Power On
Reset
Monitor
Weak
R
Pull-Up
Resistor
PAD
Output Enable
Voltage
Tolerance
Control
Hot Socket
Output
Pre-Driver
Input Buffer
to Logic Array
The POR circuit monitors the voltage level of the power supplies (V_CC, V_CCAUX, V_CCPT,
V_CCPGM, and V_CCPD) and keeps the I/O pins tri-stated until the device is in user mode.
The weak pull-up resistor (R) in the Stratix IV input/output element (IOE) keeps the
I/O pins from floating. The 3.0-V tolerance control circuit permits the I/O pins to be
driven by 3.0 V before the V_CC, V_CCAUX, V_CCPT, V_CCPGM, or V_CCPD supplies are
powered. It also prevents the I/O pins from driving out when the device is not in user
mode. To successfully power-up and exit POR on production devices, fully power
V_CC before V_CCAUX begins to ramp.
1 Altera uses GND as a reference for hot-socketing operations and I/O buffer designs.
To ensure proper operation, you must connect the GND between boards before
connecting the power supplies. This prevents the GND on your board from being
pulled up inadvertently by a path to power through other components on your board.
A pulled up GND could otherwise cause an out-of-specification I/O voltage or
current condition with the Altera device.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1