EP4SE360F35I4 Datasheet, PDF (91/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
4–11
A feature of the input register bank is to support a tap delay line. Therefore, the top
leg of the multiplier input (A) can be driven from general routing or from the cascade
chain, as shown in Figure 4–7. Table 4–9 on page 4–34 lists the DSP block dynamic
signals.
Figure 4–7. Input Register of a Half DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
scanina[17..0]
signa
signb
dataa_0[17..0]
loopback
datab_0[17..0]
+/-
dataa_1[17..0]
datab_1[17..0]
dataa_2[17..0]
datab_2[17..0]
+/-
dataa_3[17..0]
datab_3[17..0]
Delay
Register
scanouta
At compile time, you must select whether the A-input comes from general routing or
from the cascade chain. In cascade mode, the dedicated shift outputs from one
multiplier block and directly feeds the input registers of the adjacent multiplier below
it (within the same half DSP block) or the first multiplier in the next half DSP block, to
form an 8-tap shift register chain per DSP Block. The DSP block can increase the
length of the shift register chain by cascading to the lower DSP blocks. The dedicated
shift register chain spans a single column, but you can implement longer shift register
chains requiring multiple columns using the regular FPGA routing resources.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1