EP4SE360F35I4 Datasheet, PDF (105/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–25
To implement this complex multiplication within the DSP block, the real part
((a × c) – (b × d)) is implemented using two multipliers feeding one subtractor block
while the imaginary part ((a × d) + (b × c)) is implemented using another two
multipliers feeding an adder block. Figure 4–16 shows an 18-bit complex
multiplication. This mode automatically assumes all inputs are using signed
numbers.
Figure 4–16. Complex Multiplier Using Two-Multiplier Adder Mode
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
A
C
36
AxC BxD
Real Part
B
D
36
AxD BxC
Imaginary Part
Half-DSP Block
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1