EP4SE360F35I4 Datasheet, PDF (153/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
5–37
Programmable Bandwidth
Stratix IV PLLs provide advanced control of the PLL bandwidth using the PLL loop’s
programmable characteristics, including loop filter and charge pump.
Background
PLL bandwidth is the measure of the PLL’s ability to track the input clock and its
associated jitter. The closed-loop gain 3 dB frequency in the PLL determines PLL
bandwidth. Bandwidth is approximately the unity gain point for open loop PLL
response. As Figure 5–32 shows, these points correspond to approximately the same
frequency. Stratix IV PLLs provide three bandwidth settings—low, medium (default),
and high.
Figure 5–32. Open- and Closed-Loop Response Bode Plots
Open-Loop Reponse Bode Plot
0 dB
Gain
Increasing the PLL's
bandwidth in effect pushes
the open loop response out.
Closed-Loop Reponse Bode Plot
Gain
Frequency
Frequency
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1