EP4SE360F35I4 Datasheet, PDF (322/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–42
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
Guidelines for DPA-Disabled Differential Channels
When you use DPA-disabled channels in the left and right banks of a Stratix IV
device, you must adhere to the guidelines in the following sections.
1 When using non-DPA receivers, you must drive the PLL from a dedicated and
compensated clock input pin. Compensated clock inputs are dedicated clock pins in
the same I/O bank as the PLL.
f For more information about dedicated and compensated clock inputs, refer to the
Clock Networks and PLLs in Stratix IV Devices chapter.
DPA-Disabled Channels and Single-Ended I/Os
The placement rules for DPA-disabled channels and single-ended I/Os are the same
as those for DPA-enabled channels and single-ended I/Os. For more information,
refer to “DPA-Enabled Channels and Single-Ended I/Os” on page 8–38.
DPA-Disabled Channel Driving Distance
Each left and right PLL can drive all the DPA-disabled channels in the entire bank.
Using Corner and Center Left and Right PLLs
You can use a corner left and right PLL to drive all transmitter channels and a center
left and right PLL to drive all DPA-disabled receiver channels within the same
differential bank. In other words, a transmitter channel and a receiver channel in the
same LAB row can be driven by two different PLLs, as shown in Figure 8–34.
A corner left and right PLL and a center left and right PLL can drive duplex channels
in the same differential bank, as long as the channels driven by each PLL are not
interleaved. Separation is not necessary between the group of channels driven by the
corner and center left and right PLLs, as shown in Figure 8–34 and Figure 8–35.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation