EP4SE360F35I4 Datasheet, PDF (166/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–50
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Charge Pump and Loop Filter
You can reconfigure the charge-pump and loop-filter settings to update the PLL
bandwidth in real time.
Table 5–12 lists the possible settings for charge pump current (Icp) values for
Stratix IV PLLs.
Table 5–12. Charge Pump Current Bit Settings
CP[2]
0
0
0
1
CP[1]
0
0
1
1
CP[0]
0
1
1
1
Decimal Value for Setting
0
1
3
7
Table 5–13 lists the possible settings for loop-filter resistor (R) values for Stratix IV
PLLs.
Table 5–13. Loop-Filter Resistor Bit Settings
LFR[4]
LFR[3]
LFR[2]
LFR[1]
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
LFR[0]
0
1
0
0
0
1
0
0
1
0
0
Decimal Value for Setting
0
3
4
8
16
19
20
24
27
28
30
Table 5–14 lists the possible settings for loop-filter capacitor (C) values for Stratix IV
PLLs.
Table 5–14. Loop-Filter Capacitor Bit Settings
LFC[1]
LFC[0]
0
0
0
1
1
1
Decimal Value for Setting
0
1
3
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation