EP4SE360F35I4 Datasheet, PDF (334/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

9–4
Chapter 9: Hot Socketing and Power-On Reset in Stratix IV Devices
Power-On Reset Circuitry
Power-On Reset Circuitry
When power is applied to a Stratix IV device, a POR event occurs if the power supply
reaches the recommended operating range within the maximum power supply ramp
time (t_RAMP). If t_RAMP is not met, the device I/O pins and programming registers
remain tri-stated, during which device configuration could fail. The maximum t_RAMP
for Stratix IV devices is 100 ms; the minimum t_RAMP is 50 µs. When the PORSEL pin is
high, the maximum T_RAMP for Stratix IV devices is 4 ms.
Stratix IV devices provide a dedicated input pin (PORSEL) to select a POR delay time
during power up. When the PORSEL pin is connected to GND, the POR delay time is
100 to 300 ms. When the PORSEL pin is set to high, the POR delay time is 4 to 12 ms.
The POR block consists of a regulator POR, satellite POR, and main POR to check the
power supply levels for proper device configuration.
The satellite POR monitors the following:
■ V_CCPD and V_CCPGM power supplies that are used in the I/O buffers and for device
programming
■ V_CCAUX power supply which is the auxiliary supply for the programmable power
technology
■ V_CC and V_CCPT power supplies that are used in the device core
1 Altera requires powering up V_CC before V_CCAUX.
The main POR waits for satellite POR and the regulator POR to release the POR
signal. Until the release of the POR signal, the device configuration cannot start.
The internal configuration memory supply that is used during device configuration is
checked by the regulator POR block and is gated in the main POR block for the final
POR trip. Figure 9–2 shows a simplified diagram of the POR block.
1 All configuration-related dedicated and dual function I/O pins must be powered by
V_CCPGM.
Figure 9–2. Simplified POR Diagram for Stratix IV Devices
Regulator POR
V_CCPGM
V_CCPD
V_CC
V_CCPT
V_CCAUX
Satellite POR
PORSEL
Main POR
POR Pulse
Setting
POR
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation