EP4SE360F35I4 Datasheet, PDF (109/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–29
Multiply Accumulate Mode
In multiply accumulate mode, the second-stage adder is configured as a 44-bit
accumulator or subtractor. The output of the DSP block is looped back to the
second-stage adder and added or subtracted with the two outputs of the first-stage
adder block according to Equation 4–3 on page 4–5. Figure 4–19 shows the DSP block
configured to operate in multiply accumulate mode.
Figure 4–19. Multiply Accumulate Mode Shown for a Half DSP Block
accum_sload
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
output_round
output_saturate
chainout_sat_overflow (1)
dataa_0[ ]
datab_0[ ]
+
dataa_1[ ]
datab_1[ ]
dataa_2[ ]
44
+
result[ ]
datab_2[ ]
+
dataa_3[ ]
datab_3[ ]
Half-DSP Block
Note to Figure 4–19:
(1) Block output for saturation overflow of chainout.
A single DSP block can implement up to two independent 44-bit accumulators.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1