EP4SE360F35I4 Datasheet, PDF (264/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–40
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–23 shows a simple block diagram of the DLL. The input reference clock goes
into the DLL to a chain of up to 16 delay elements. The phase comparator compares
the signal coming out of the end of the delay chain block to the input reference clock.
The phase comparator then issues the upndn signal to the Gray-code counter. This
signal increments or decrements a six-bit delay setting (DQS delay settings) that
increases or decreases the delay through the delay element chain to bring the input
reference clock and the signals coming out of the delay element chain in phase.
Figure 7–23. Simplified Diagram of the DQS Phase-Shift Circuitry ⁽¹⁾
addnsub
Phase offset settings
from the logic array
( offset [5:0] )
DLL
Input Reference
Clock (2)
clk
aload
upndnin
Phase
Up/Down
Comparator upndninclkena Counter
offsetdelayctrlout [5:0]
offsetdelayctrlout [5:0]
Delay Chains
6
delayctrlout [5:0]
6
Phase
Offset
6
Control
offsetdelayctrlin [5:0]
A
(dll_offset_ctrl_a)
Phase offset
settings to DQS pins
on top or bottom edge (3)
( offsetctrlout [5:0] )
addnsub
Phase offset settings
from the logic array ( offset [5:0] )
6
Phase
Offset
Control
B
6
offsetdelayctrlin [5:0]
(dll_offset_ctrl_b)
Phase offset
settings to DQS pin
on left or right edge (3)
( offsetctrlout [5:0] )
DQS Delay
6
Settings (4)
6
dqsupdate
Notes to Figure 7–23:
(1) All features of the DQS phase-shift circuitry are accessible from the ALTMEMPHY megafunction in the Quartus II software.
(2) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer
to Table 7–5 on page 7–33 through Table 7–17 on page 7–39.
(3) Phase offset settings can only go to the DQS logic blocks.
(4) DQS delay settings can go to the logic array, DQS logic block, and leveling circuitry.
1 In the Quartus II assignment, phase offset control block ‘A’ is designated as
DLLOFFSETCTRL_<coordinate x>_<coordinate y>_N1 and phase offset control block
‘B’ is designated as DLLOFFSETCTRL_<coordinate x>_<coordinate y>_N2.
You can reset the DLL from either the logic array or a user I/O pin. Each time the DLL
is reset, you must wait for 1,280 clock cycles for the DLL to lock before you can
capture the data properly.
Depending on the DLL frequency mode, the DLL can shift the incoming DQS signals
by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°, 120°, 135°, 144°, 180°, or 240°. The
shifted DQS signal is then used as the clock for the DQ IOE input registers.
All DQS/CQ and CQn pins, referenced to the same DLL, can have their input signal
phase shifted by a different degree amount but all must be referenced at one
particular frequency. For example, you can have a 90° phase shift on DQS1T and a 60°
phase shift on DQS2T, referenced from a 200-MHz clock. Not all phase-shift
combinations are supported. The phase shifts on the DQS pins referenced by the same
DLL must all be a multiple of 22.5° (up to 90°), 30° (up to 120°), 36° (up to 144°), 45°
(up to 180°), or 60° (up to 240°).
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation