EP4SE360F35I4 Datasheet, PDF (311/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
8–31
Source-Synchronous Timing Budget
This section describes the timing budget, waveforms, and specifications for
source-synchronous signaling in the Stratix IV device family. LVDS I/O standards
enable high-speed data transmission. This high data transmission rate results in better
overall system performance. To take advantage of fast system performance, it is
important to understand how to analyze timing for these high-speed signals. Timing
analysis for the differential block is different from traditional synchronous timing
analysis techniques.
Instead of focusing on clock-to-output and setup times, source synchronous timing
analysis is based on the skew between the data and the clock signals. High-speed
differential data transmission requires the use of timing parameters provided by IC
vendors and is strongly influenced by board skew, cable skew, and clock jitter. This
section defines the source-synchronous differential data orientation timing
parameters, the timing budget definitions for the Stratix IV device family, and how to
use these timing parameters to determine a design’s maximum performance.
Differential Data Orientation
There is a set relationship between an external clock and the incoming data. For
operations at 1 Gbps and a serialization factor of 10, the external clock is multiplied by
10. You can set phase-alignment in the PLL to coincide with the sampling window of
each data bit. The data is sampled on the falling edge of the multiplied clock.
Figure 8–25 shows the data bit orientation of the ×10 mode.
Figure 8–25. Bit Orientation in the Quartus II Software
inclock/outclock
data in
MSB
10 LVDS Bits
LSB
9 87 6543210
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at high
frequencies. Figure 8–26 shows the data bit orientation for a channel operation. This
figure is based on the following:
■ Serialization factor equals the clock multiplication factor
■ Edge alignment is selected for phase alignment
■ Implemented in hard SERDES
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1