EP4SE360F35I4 Datasheet, PDF (58/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

3–2
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
Table 3–1. Summary of TriMatrix Memory Features (Part 2 of 2)
Feature
MLABs
Configurations
(depth × width)
64 × 8
64 × 9
64 × 10
32 × 16
32 × 18
32 × 20
Parity bits
Byte enable
Packed mode
Address clock enable
Single-port memory
Simple dual-port memory
True dual-port memory
Embedded shift register
ROM
FIFO buffer
Simple dual-port mixed
width support
True dual-port mixed width
support
Memory Initialization File
(.mif)
Mixed clock mode
Power-up condition
Register clears
Write/Read operation
triggering
Supported
Supported
—
Supported
Supported
Supported
—
Supported
Supported
Supported
—
—
Supported
Supported
Outputs cleared if
registered, otherwise reads
memory contents
Output registers
Write: Falling clock edges
Read: Rising clock edges
Same-port read-during-write Outputs set to don’t care
Mixed-port read-during-write
Outputs set to old data,
new data, or don’t care ⁽¹⁾
ECC Support
Soft IP support using the
Quartus II software
M9K Blocks
8K × 1
4K × 2
2K × 4
1K × 8
1K × 9
512 × 16
512 × 18
256 × 32
256 × 36
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Outputs cleared
Output registers
Write and Read: Rising clock
edges
Outputs set to old data or
new data
Outputs set to old data or
don’t care
Soft IP support using the
Quartus II software
M144K Blocks
16K × 8
16K × 9
8K × 16
8K × 18
4K × 32
4K × 36
2K × 64
2K × 72
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Outputs cleared
Output registers
Write and Read: Rising clock
edges
Outputs set to old data or
new data
Outputs set to old data or
don’t care
Built-in support in ×64-wide
SDP mode or soft IP support
using the Quartus II software
Note to Table 3–1:
(1) The mixed-port read-during-write options of new data or old data are only supported for MLABs when you use both the read address registers
and the output registers.
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation