EP4SE360F35I4 Datasheet, PDF (272/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–48
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
1 The ALTMEMPHY megafunction dynamically calibrates the alignment for read- and
write-leveling during the initialization process.
f For more information about the ALTMEMPHY megafunction, refer to the External
Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide.
Dynamic On-Chip Termination Control
Figure 7–30 shows the dynamic OCT control block. The block includes all the registers
needed to dynamically turn on OCT RT during a read and turn OCT RT off during a
write.
f For more information about dynamic on-chip termination control, refer to the I/O
Features in Stratix IV Devices chapter.
Figure 7–30. Stratix IV Dynamic OCT Control Block
OCT Control
2
OCT Half-
DFF
Rate Clock
OCT Enable
DFF
HDR
Block
Resynchronization
Registers
OCT Control Path
Write
Clock (1)
Note to Figure 7–30:
(1) The write clock comes from either the PLL or the write-leveling delay chain.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation