EP4SE360F35I4 Datasheet, PDF (370/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–34
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
You can use a download cable to configure multiple Stratix IV devices by connecting
each device’s nCEO pin to the subsequent device’s nCE pin. The first device’s nCE pin is
connected to GND, while its nCEO pin is connected to the nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while its nCEO pin is
left floating. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and
CONF_DONE) are connected to every device in the chain. Because all CONF_DONE pins are
tied together, all devices in the chain initialize and enter user mode at the same time.
In addition, because the nSTATUS pins are tied together, the entire chain halts
configuration if any device detects an error. The Auto-restart configuration after
error option does not affect the configuration cycle because you must manually restart
the configuration in the Quartus II software when an error occurs.
Figure 10–15 shows how to configure multiple Stratix IV devices with a download
cable.
Figure 10–15. Multi-Device PS Configuration Using a USB Blaster, EthernetBlaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV Cable
V_CCPGM (1)
10 kΩ
V_CCPGM (1)
Stratix IV Device 1
V_CCPGM (1) ^VCCPGM ⁽¹⁾
CONF_DONE
10 kΩ (2)
MSEL2
MSEL1
MSEL0
nSTATUS
DCLK
10 kΩ
V_CCPGM (1)
10 kΩ
GND
nCE
GND
DATA0
nCONFIG
nCEO
V_CCPGM (1)
10 kΩ (2)
Download Cable
10-Pin Male Header
(PS Mode)
Pin 1
V_CCPGM (1)
GND
V_IO (3)
GND
Stratix IV Device 2
V_CCPGM (1)
CONF_DONE
MSEL2
MSEL1
MSEL0
nSTATUS
DCLK
GND
nCE
DATA0
nCONFIG
nCEO N.C.
Notes to Figure 10–15:
(1) Connect the pull-up resistor to the same supply voltage (V_CCPGM) as the USB Blaster, MasterBlaster (VIO pin), ByteBlaster II, ByteBlasterMV, or
EthernetBlaster cable.
(2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This is to
ensure that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need
the pull-up resistors on DATA0 and DCLK.
(3) Pin 6 of the header is a V_IO reference voltage for the MasterBlaster output driver. V_IO must match the device’s V_CCPGM. For more information about
this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cables,
this pin is a no connect.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation