EP4SE360F35I4 Datasheet, PDF (48/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

2–12
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, wide
parity functions, and comparators. The ALM in arithmetic mode uses two sets of
2 four-input LUTs along with two dedicated full adders. The dedicated adders allow
the LUTs to be available to perform pre-adder logic; therefore, each adder can add the
output of 2 four-input functions.
The four LUTs share dataa and datab inputs. As shown in Figure 2–10, the carry-in
signal feeds to adder0 and the carry-out from adder0 feeds to the carry-in of adder1.
The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in
arithmetic mode can drive out registered and/or unregistered versions of the adder
outputs.
Figure 2–10. ALM in Arithmetic Mode
carry_in
datae0
dataf0
datac
datab
dataa
4-Input
LUT
4-Input
LUT
adder0
DQ
reg0
To general or
local routing
To general or
local routing
datad
datae1
dataf1
4-Input
LUT
4-Input
LUT
adder1
DQ
reg1
To general or
local routing
To general or
local routing
carry_out
While operating in arithmetic mode, the ALM can support simultaneous use of the
adder’s carry output along with combinational logic outputs. In this operation, adder
output is ignored. Using the adder with combinational logic output provides resource
savings of up to 50% for functions that can use this ability.
Arithmetic mode also offers clock enable, counter enable, synchronous up/down
control, add/subtract control, synchronous clear, and synchronous load. The LAB
local interconnect data inputs generate the clock enable, counter enable, synchronous
up/down, and add/subtract control signals. These control signals are good
candidates for the inputs that are shared between the four LUTs in the ALM. The
synchronous clear and synchronous load options are LAB-wide signals that affect all
registers in the LAB. These signals can also be individually disabled or enabled per
register. The Quartus II software automatically places any registers that are not used
by the counter into other LABs.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation