EP4SE360F35I4 Datasheet, PDF (132/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–16
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
You can set the input clock sources and the clkena signals for the GCLK and RCLK
network multiplexers through the Quartus II software using the ALTCLKCTRL
megafunction. You can also enable or disable the dedicated external clock output pins
using the ALTCLKCTRL megafunction. Figure 5–13 shows the external PLL output
clock control block.
1 When using the ALTCLKCTRL megafunction to implement dynamic clock source
selection, the inputs from the clock pins feed the inclk[0..1] ports of the multiplexer,
while the PLL outputs feed the inclk[2..3] ports. You can choose from among these
inputs using the CLKSELECT[1..0] signal.
f For more information, refer to the Clock Control Block (ALTCLKCTRL) Megafunction
User Guide.
Figure 5–13. Stratix IV External PLL Output Clock Control Block
PLL Counter
Outputs
7 or 10
Static Clock Select (1)
Enable/
Disable
Internal
Logic
IOE (2)
Internal
Logic
Static Clock
Select (1)
PLL_<#>_CLKOUT pin
Notes to Figure 5–13:
(1) When the device is operation in user mode, you can only set the clock select signals through a configuration file (.sof
or .pof) and cannot be dynamically controlled.
(2) The clock control block feeds to a multiplexer within the PLL_<#>_CLKOUT pin’s IOE. The PLL_<#>_CLKOUT
pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control
block.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation