EP4SE360F35I4 Datasheet, PDF (225/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

February 2011
SIV51007-3.2
SIV51007-3.2
7. External Memory Interfaces in
Stratix IV Devices
This chapter describes external memory interfaces available with the Stratix^ IV
device family and that family’s silicon capability to support external memory
interfaces. To support the level of system bandwidth achievable with Altera^
Stratix IV FPGAs, the devices provide an efficient architecture to quickly and easily fit
wide external memory interfaces within their small modular I/O bank structure. The
I/Os are designed to provide high-performance support for existing and emerging
external double data rate (DDR) memory standards, such as DDR3, DDR2, DDR
SDRAM, QDR II+, QDR II SRAM, and RLDRAM II.
Stratix IV I/O elements provide easy-to-use built-in functionality required for a rapid
and robust implementation with features such as dynamic calibrated on-chip
termination (OCT), trace mismatch compensation, read- and write-leveling circuit for
DDR3 SDRAM interfaces, half data rate (HDR) blocks, and 4- to 36-bit programmable
DQ group widths.
The high-performance memory interface solution is backed-up by a self-calibrating
megafunction (ALTMEMPHY), optimized to take advantage of the Stratix IV I/O
structure and the TimeQuest Timing Analyzer, which completes the picture by
providing the total solution for the highest reliable frequency of operation across
process, voltage, and temperature (PVT) variations.
This chapter contains the following sections:
■ “Memory Interfaces Pin Support” on page 7–3
■ “Stratix IV External Memory Interface Features” on page 7–29
f For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to the External Memory Interface Handbook.
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are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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Stratix IV Device Handbook
Volume 1
February 2011
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