EP4SE360F35I4 Datasheet, PDF (243/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–19
Figure 7–14. Number of DQS/DQ Groups per Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the
1517-Pin FineLine BGA Package ⁽¹⁾, ⁽²⁾, ⁽³⁾, ⁽⁴⁾, ⁽⁵⁾
DLL0
I/O Bank 1A
43 User I/Os
x4=5
x8/x9=1
x16/x18=0
I/O Bank 1C
20 User I/Os
x4=0
x8/x9=0
x16/x18=0
I/O Bank 2C
21 User I/Os
x4=1
x8/x9=0
x16/x18=0
I/O Bank 2A
46 User I/Os
x4=6
x8/x9=2
x16/x18=1
DLL1
I/O Bank 8A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 3A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 8B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 7B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices
in the 1517-Pin FineLine BGA
I/O Bank 3B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 6A
44 User I/Os
x4=5
x8/x9=1
x16/x18=0
I/O Bank 6C
21 User I/Os
x4=0
x8/x9=0
x16/x18=0
I/O Bank 5C
21 User I/Os
x4=0
x8/x9=0
x16/x18=0
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 5A
46 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–14:
(1) These numbers are preliminary until the devices are available.
(2) EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 devices do not support 32/36 mode. To interface with a 36 QDR II+/QDR II SRAM
device, refer to “Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R_UP and R_DN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as R_UP and R_DN pins for OCT calibration. If two pins of a ×4 group are used as R_UP and R_DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a 4 DQS/DQ group with any of its pin members
used for configuration purposes. Make sure that the DQS/DQ groups that you have chosen are not used for configuration as you may lose up to
four 4 DQS/DQ groups, depending on your configuration scheme.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1