EP4SE360F35I4 Datasheet, PDF (318/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–38
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
Differential Pin Placement Guidelines
To ensure proper high-speed operation, differential pin placement guidelines have
been established. The Quartus II compiler automatically checks that these guidelines
are followed and issues an error message if they are not met.
This section is divided into pin placement guidelines with and without DPA usage
because DPA usage adds some constraints on the placement of high-speed differential
channels.
1 DPA-enabled differential channels refer to DPA mode or soft-CDR mode; DPA
disabled channels refer to non-DPA mode.
Guidelines for DPA-Enabled Differential Channels
The Stratix IV device family has differential receivers and transmitters in I/O banks
on the left and right sides of the device. Each receiver has a dedicated DPA circuit to
align the phase of the clock to the data phase of its associated channel. When you use
DPA-enabled channels in differential banks, you must adhere to the guidelines listed
in the following sections.
DPA-Enabled Channels and Single-Ended I/Os
When you enable a DPA channel in a bank, both single-ended I/Os and differential
I/O standards are allowed in the bank.
■ Single-ended I/Os are allowed in the same I/O bank, as long as the single-ended
I/O standard uses the same V_CCIO as the DPA-enabled differential I/O bank.
■ Single-ended inputs can be in the same logic array block (LAB) row as a
differential channel using the SERDES circuitry.
■ DDIO can be placed within the same LAB row as a SERDES differential channel
but half rate DDIO (single data rate) output pins cannot be placed within the same
LAB row as a receiver SERDES differential channel. The input register must be
implemented within the FPGA fabric logic.
DPA-Enabled Channel Driving Distance
If the number of DPA channels driven by each left and right PLL exceeds 25 LAB
rows, Altera recommends implementing data realignment (bit slip) circuitry for all
the DPA channels.
Using Corner and Center Left and Right PLLs
If a differential bank is being driven by two left and right PLLs, where the corner left
and right PLL is driving one group and the center left and right PLL is driving
another group, there must be at least one row of separation between the two groups of
DPA-enabled channels (refer to Figure 8–31). The two groups can operate at
independent frequencies.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation